1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a bit line sense amplifier control circuit and a semiconductor memory apparatus having the same.
2. Related Art
In a semiconductor memory apparatus, specifically, a DRAM, when reading information of a memory cell or writing information to the memory cell, in order to sufficiently amplify a signal of data to be read or written, a bit line sense amplifier is used.
FIG. 1 is a configuration diagram illustrating a known bit line sense amplifier and control circuit therefor.
A bit line sense amplifier 10 may be configured in a type of a latch which is connected between a bit line pair BL and BLB. The bit line sense amplifier 10 amplifies a difference of the voltage levels of the bit line pair BL and BLB by using, as power sources, sense amplifier power signals RTO and SB outputted from a bit line sense amplifier control circuit 12.
The bit line sense amplifier control circuit 12 includes a sense amplifier driver 121 which is configured to generate the sense amplifier power signals RTO and SB in response to a first sense amplifier enable signal SAP and a second sense amplifier enable signal SAN.
The sense amplifier driver 121 includes a first driver P1 and a second driver N1. The first driver has a source terminal connected to a core voltage supply terminal VCORE, is driven by the first sense amplifier enable signal SAP and outputs the first sense amplifier power line signal RTO through a drain terminal. The second driver N1 has a source terminal connected to a ground terminal VSS, is driven by the second sense amplifier enable signal SAN and outputs the second sense amplifier power line signal SB through a drain terminal.
In a read operation for a memory cell, the data sensed by the bit line sense amplifier 10 should be transferred to a main amplifier (not shown). Here, since a load by a data line is substantial, latching capability of the bit line sense amplifier 10 should be strong so as not to lose the information sensed by the bit line sense amplifier 10. Also, in order to load information with sufficient charges on the data line, the driving force of the bit line sense amplifier 10 should be strong.
Conversely, in a write operation, if the latching capability of the bit line sense amplifier 10 increase, a duration of the write operation may increase. For example, data to write may have an opposite level to the data currently stored in the bit line sense amplifier 10. In this case, a toggling of a data level may take a longer time, and thus the duration of the write operation may increase.
As a result, a bit line sense amplifier, which has strong latching capability and driving force in a read operation and appropriate latching capability in a write operation, is demanded.